Parallel computers include many components, and thus fail highly frequently. Accordingly, it is necessary to be able to operate a parallel computer without replacing a node that has failed so as to reduce the maintenance time consumed to replace the node that has failed. In order to meet this requirement in a multidimensional torus connection network, it is necessary to perform communications using routes not involving a node that has failed. However, having irregularity in the ways of using communication routes, wherein communications are performed through alternative routes when a failure has occurred, requires provision of an additional virtual channel to avoid deadlock. Also, this use increases the load on receiving processes because packets arrive in a mixed-up order. In other words, when alternative routes are formed adaptively for transmitting packets, a packet and its subsequent packet are sometimes transmitted through different routes, which have different traffic levels, and one of those packets may be delayed in transfer. This causes the receiver side to receive packets in a mixed-up order and to be required to perform a process of rearranging those packets into the right order. This increases the load on the receiving process.
In Patent Document 1 many virtual channels are used, and communications routes for each channel are statically determined, including alternative routes, and thereby failures are avoided promptly while attaining a deadlock-free condition.
It is known that connecting nodes for parallel computers not in linear but in a ring configuration, i.e., a torus, increases communications speed for parallel computing. Especially in remote communications algorithms, the performance of a torus becomes twice that of a mesh of the same size. In other words, the communication that takes the longest time in a torus is a communication from one node to another node that is half the length of the whole ring away, making the communications length ½ of the whole circle because one end and another end are connected, while a communication route from one end to another end in a mesh network is the communications route that takes the longest time. Accordingly, when a parallel computer is compartmentalized, or processors are grouped and the groups are connected separately, the groups of processors have to be connected in a torus.
In Patent Document 2, a switch with six ports is used, and a compartmentalized mesh, i.e., groups in which processors are connected in a mesh configuration, are connected in a torus. The two ports are connected to both ends of the compartmentalized mesh, and the four ports connect switches in an expanded torus.
Implementation of wiring between circuit boards costs more than that within a single circuit board, and the dimensions for connecting mother boards are limited in terms of actual implementation. Thus, one circuit board is handled as a group, and dimensions are increased only in the circuit board so that parallel computation of high-dimensional data can be performed at a high speed. QCDOC is a parallel computer having this configuration, and it was co-developed by RIKEN, Japan, Columbia University, U.S., and Brookhaven National Laboratory, U.S. According to QCDOC, mother boards that each include sixty-four processors connected in a six-dimensional hypercube are connected to each other using three of the six dimensions of the a six-dimensional hypercube. In the six-dimensional space in the inter-processor connections according to QCDOC, three-dimensional distances between mother boards are long, and remaining three-dimensional distances inside the mother boards, are 2.
Adaptive determination of failure-avoiding routes causes packets to arrive in a mixed-up order and leads to an increase in delay in the receiving process. This also increases a load. With these costs comes and increase in efficiency in using the band, which reduces to the minimum number of virtual channels to be added. By contrast, static determination of failure-avoiding routes leads to a decrease in delay in the receiving process and to a reduction in load, but requires a greater number of virtual channels to be added.
In some failure-avoiding communications methods in conventional techniques, different normal communications routes are used as failure-avoiding routes. When a band is shared by a normal communications route and a failure-avoiding route, the performance is deteriorated.
Torus compartmentalization according to conventional techniques divides a ring to generate straight connections, reforms the ring as a closed ring by using switches. In such a case, routers need ports for switching. However, only one switching target port is used at a time, which deteriorates the efficiency.
FIG. 1 illustrates the expanded torus connection disclosed by Patent Document 2.
In FIG. 1, numerical symbol 10 denotes 6-port switches, and numerical symbol 11 denotes processors. A mesh compartmentalized by eight processors 11 is connected to each of the switches 10, and a torus can be closed when its size is a multiple of eight (when the number of the included processors 11 is a multiple of eight) according to a setting in each switch 10.
In Patent Document 3, a system in which a plurality of buffers are provided in a node in an N-dimensional network for performing communications is disclosed.    Patent Document 1: Japanese Laid-open Patent Publication No. 6-266684    Patent Document 2: Japanese Laid-open Patent Publication No. 2005-174289    Patent Document 3: Japanese Patent No. 3532574    Non Patent Document 1: “The QCDOC supercomputer: hardware, software, and performance”, P. A. Boylea, b, C. Junga, c, and T. Wettigd, CHEP03, La Jolla, Calif., Mar. 24-28, 2003, phys.columbia.edu/˜cqft/